View CY8C9520A_5665926.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY8C9520A cy8c9540a, cy8c9560a 20, 40, and 60 bit i/o expander with eeprom cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ?408-943-2600 document number: 38-12036 rev. *e revised december 14, 2010 features i 2 c interface logic electrically compatible with smbus up to 20 (CY8C9520A), 40 (cy8c9540a), or 60 (cy8c9560a) i/o data pins independently configurable as inputs, outputs, bi-directional input/outputs, or pwm outputs 4/8/16 pwm sources with 8-bit resolution extendable soft addressing algorithm allowing flexible i 2 c address configuration internal 3-/11-/27-kbyte eeprom user default storage, i/o port settings in internal eeprom optional eeprom write disable (wd) input interrupt output indicates input pin level changes and pulse width modulator (pwm) state changes internal power on reset (por) internal configurable watchdog timer top level block diagram overview the cy8c95xxa is a multi-port i/o expander with on board user available eeprom and several pw m outputs. all devices in this family operate identically but differ in i/o pins, number of pwms, and internal eeprom size. the cy8c95xxa operates as two i 2 c slave devices. the first device is a multi port i/o expander (single i 2 c address to access all ports through registers). the second device is a serial eeprom. dedicated configuratio n registers can be used to disable the eeprom. the eeprom uses 2-byte addressing to support the 28 kbyte eeprom address space. the selected device is defined by the most significant bits of the i 2 c address or by specific register addressing. the i/o expander's data pins can be independently assigned as inputs, outputs, quasi-bidirectional input/outputs or pwm ouputs. the individual data pins can be configured as open drain or collector, strong drive (10 ma source, 25 ma sink), resistively pulled up or down, or high impedanc e. the factory default config- uration is pulled up internally. the system master writes to th e i/o configuration registers through the i 2 c bus. configuration and output register settings are storable as user defaults in a dedicated section of the eeprom. if user defaults were stored in eeprom, they are restored to the ports at power up . while this device can share the bus with smbus devices, it c an only communicate with i 2 c masters. the i 2 c slave in this device requires that the i 2 c master supports clock stretching. there is one dedicated pin that is configured as an interrupt output (int) and can be connecte d to the interrupt logic of the system master. this signal can in form the system master that there is incoming data on its ports or that the pwm output state was changed. the eeprom is byte readable and supports byte-by-byte writing. a pin can be config ured as an eeprom write disable (wd) input that blocks write o perations when set high. the configuration regist ers can also disable eeprom operations. the cy8c95xxa has one fixed address pin (a0) and up to six additional pins (a1-a6), which allow up to 128 devices to share a common two wire i 2 c data bus. the extendable soft addressing algorithm provides the option to choose the number of pins needed to assign the desired address. pins not used for address bits are available as gpio pins. there are 4 (CY8C9520A), 8 (cy8c9540a), or 16 (cy8c9560a) independently configurable 8-bit pwms. these pwms are listed as pwm0-pwm15. each pwm can be clocked by one of six available clock sources. for details on how to configure i 2 c, see application note "communication - i 2 c port expander with flash storage - an2304" at http://www.cypress.com. eeprom user settings are a user available are a control unit gpor t 0 gpor t 1 gpor t 2 gpor t 3 gpor t 7 pwm 0 pwm 15 power-on-reset 1.5 mhz 93.75 khz divider (1-255) clocks 32 khz 24 mhz wd scl sda v dd v ss 8 bit io 5 bit io 3 bit io or a4-a6 4 bit io or a1-a3, wd6 8 bit io 8 bit io int a0 [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 2 of 32 contents architecture .............................................................3 applications ........................................................3 device access addressing ....................................4 serial eeprom device .. ............. ............. ..........4 multi port i/o device ...........................................4 document conventions ..........................................4 acronyms ............................................................4 units of measure ................................................4 numeric naming .................................................4 pinouts .....................................................................5 28-pin part pinout ..............................................5 48-pin part pinout ..............................................6 100-pin part pinout ............................................7 pin descriptions ......................................................9 extendable soft addressing ...............................9 interrupt pin (int) ...............................................9 write disable pin (wd) .......................................9 external reset pin (xres) .................................9 working with pwms ...........................................9 register mapping table ........................................11 register descriptions ...........................................11 input port registers (00h - 07h) .......................11 output port registers (08h - 0fh) ....................11 int. status port registers (10h - 17h) ...............12 port select register (18h) ................................12 interrupt mask port regist er (19h) ...................12 select pwm register (1ah) ..............................12 inversion register (1bh) ...................................12 port direction register (1ch) ...........................12 drive mode registers (1dh -23h) ......................12 pwm select register (28h) ..............................12 config (29h) ......................................................13 period register (2ah) .......................................13 pulse width register (2bh) ..............................13 divider register (2ch) ......................................13 enable register (2dh) ......................................13 device id/status register (2eh) .......................13 watchdog register (2fh) .................................14 command register (30h) .................................14 commands description ........................................14 store config to e2 por defaults cmd (01h) ...14 restore factory defaults cmd (02h) ................14 write e2 por defaults cmd (03h) ...................14 read e2 por defaults cmd (04h) ...................15 write device config cmd (05h) ........................15 read device config cmd (06h) ........................15 reconfigure device cmd (07h) ........................15 electrical specifications .......................................16 absolute maximum ratings ..............................16 operating temperature ....................................16 dc electrical characteristics ............................17 ac electrical characteristics ............................19 packaging dimensions .........................................21 thermal impedances ........................................23 solder reflow peak temp erature ....................23 features and ordering information .....................24 ordering code definitions ................................24 acronyms ...............................................................25 reference documents ..........................................25 document conventions ........................................25 units of measure ..............................................25 numeric conventions .......................................25 glossary .................................................................26 document history page ... .....................................31 sales, solutions, and legal information .............32 worldwide sales and design support ..............32 products ...........................................................32 psoc solutions ................................................32 [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 3 of 32 architecture the top level block diagram on page 1 illustrates the device block diagram. the main blocks in clude the control unit, pwms, eeprom, and i/o ports. the cont rol unit executes commands received from the i 2 c bus and transfers data between other bus devices and the master device. the on chip eeprom can be separated conventionally into two regions. the first region is designed to store data and is available for byte wide read/writes through the i 2 c bus. it is possible to prevent write operations by se tting the wd pin to high. all eeprom operations can be blo cked by configuration register settings. the second region allows the user to store the port and pwm default settings using spec ial commands. these defaults are automatically reloaded and pr ocessed after device power on. the number of i/o lines and pwm sources are listed in the following table. there are four pins on gport 2 and three on gport 1 that can be used as general purpose i/o or eeprom write disable (wd) and i 2 c-address input (a1-a6), depending on configuration settings. figure 1 shows the single port logica l structure. the port drive mode register gives the option to select one of seven available modes for each pin separately: pulled up/down, open drain high/low, strong drive fast/slow, or high impedance. by default these configuration registers stor e values setting i/o pins to be pulled up. the invert register enables inversion of the logic of the input registers separately for each pin. the select pwm register assigns pins as pwm outputs. all of these configuration registers are read/writable using corresponding commands in the multi-port device. figure 1. logical structure of the i/o port the port input and output registers are separated. when the output register is written, the da ta is sent to the external pins. when the input register is read, the external pin logic levels are captured and transferred. as a result, the read data can be different from written output re gister data. this enables imple- mentation of a quasi-bidirectional input-output mode, when the corresponding binary digit is configured as pulled up/down output. each port has an interrupt mask register and an interrupt status register. each high bit in the interrupt status register signals that there has been a change in the corresponding input line since the last read of that interrupt st atus register. the interrupt status register is cleared after each read. the interrupt mask register enables/disables activation of the int line when input levels are changed. each high in the interrupt mask register masks (disables) an interrupt generated from the corresponding input line. applications each gpio pin can be used to monitor and control various board level devices, including leds and system intrusion detection devices. the on board eeprom can be used to store information such as error codes or board manufacturing data for read-back by application software for diagnostic purposes. table 1. gpio availability port CY8C9520A cy8c9540a cy8c9560a gport 0 8 bit 8 bit 8 bit gport 1 5-8 bit [1] 5-8bit [1] 5-8 bit [1] gport 2 0-4 bit [1] 0-4it [1] 0-4 bit [1] gport 3 ? 8 bit 8 bit gport 4 ? 8 bit 8 bit gport 5 ? 4 bit 8 bit gport 6 ? ? 8 bit gport 7 ? ? 8 bit pwms 4 8 16 note 1. this port contains configuration-dependant gpio lines or a1-a6 and wd lines. gportx 7 drive mode registers drive mode pull-up drive mode hig h z interrupt status interrupt mask pin direction inversion input register select pwm output register 8 bit io data pwms [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 4 of 32 device access addressing following a start condition, the i 2 c master device sends a byte to address an i 2 c slave. this address acce sses the device in the cy8c95xx. by default there are two possible address formats in binary representation: 010000a0x and 101000a0x. the first is used to access the multi port de vice and the second to access the eeprom. if additional address lines (a1-a6) are used then the device addressing. ta b l e 2 defines the device addresses. this addressing method uses a technique called extendable soft addressing, described in the section extendable soft addressing on page 9 . when all address lines a1-a6 are used, the device being accessed is defined by the first byte following the address in the write transaction. if the most significant bit (msb) of this byte is ?0?, this byte is treated as a command (register address) byte of the multi-port device. if the msb is ?1?, this byte is the first of a 2-byte eeprom address. in this case, the device masks the msb to determine the eeprom address. serial eeprom device eeprom reading and writing oper ations require 2 bytes, ahi and alo, which indicate the memory address to use. to read one or more bytes, the master device addresses the unit with a write cycle (= 0) to send ahi followed by alo, readdresses the unit with a read cycle (= 1), and reads one or more data bytes. each data byte read increments the internal address counter by one up to the end of the eeprom address space. a read or write beyond the end of the eeprom ad dress space must result in a nak response by the port expander. to write data to the eeprom, the master device performs one write cycle, with the first two bytes being ahi followed by alo. this is followed by one or more data bytes. in the case of block writing it is advisable to set the starting address on the beginning of the 64-byte boundary, for exam ple 01c0h or 0080h, but this is not mandatory. when a 64-byte boundary is crossed in the eeprom, the i 2 c clock is stretched wh ile the device performs an eeprom write sequence. if the end of available eeprom space is reached, then further writes are responded to with a nak. refer to figure 6 on page 10, which illustrates memory reading and writing procedures for the eeprom device. multi port i/o device this device allows the user to set configurations and i/o opera- tions through internal registers. each data transfer is preceded by the command byte. this byte is used as a pointer to a register that receives or transmits data. available registers are listed in table 7 on page 11. document conventions acronyms ta b l e 3 lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 17 on page 16 lists all the abbreviations used in section 4. numeric naming hexidecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or ?0x? are decimal. table 2. device addressing multi-port device eeprom device 01 0 0 0 0 a 0 r/w 10 1 00 0a 0 r/w 01000a 1 a 0 r/w 10 1 00a 1 a 0 r/w 0100a 2 a 1 a 0 r/w 10 1 0a 2 a 1 a 0 r/w 010a 3 a 2 a 1 a 0 r/w 10 1a 3 a 2 a 1 a 0 r/w 01a 4 a 3 a 2 a 1 a 0 r/w 10a 4 a 3 a 2 a 1 a 0 r/w 0a 5 a 4 a 3 a 2 a 1 a 0 r/w 1a 5 a 4 a 3 a 2 a 1 a 0 r/w a 6 a 5 a 4 a 3 a 2 a 1 a 0 r/w a 6 a 5 a 4 a 3 a 2 a 1 a 0 r/w table 3. acronyms acronym description ac alternating current dc direct current eeprom electrically erasable programmable read-only memory (e 2 ) gpio general purpose i/o i/o input/output msb most-significant bit por power on reset pwm pulse width modulator [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 5 of 32 pinouts the cy8c95xxa device is available in a variety of packages , which are listed and illustrated in the following tables. 28-pin part pinout table 4. 28-pin part pinout (ssop) pin no. pin name description figure 2. CY8C9520A 28-pin device 1 gport0_bit0_pwm3 port 0, bit 0, pwm 3. 2 gport0_bit1_pwm1 port 0, bit 1, pwm 1. 3 gport0_bit2_pwm3 port 0, bit 2, pwm 3. 4 gport0_bit3_pwm1 port 0, bit 3, pwm 1. 5 gport0_bit4_pwm3 port 0, bit 4, pwm 3. 6 gport0_bit5_pwm1 port 0, bit 5, pwm 1. 7 gport0_bit6_pwm3 port 0, bit 6, pwm 3. 8 gport0_bit7_pwm1 port 0, bit 7, pwm 1. 9v ss ground connection. 10 i 2 c serial clock (scl) i 2 c clock. 11 i 2 c serial data (sda) i 2 c data. 12 gport2_bit3_pwm3/a1 port 2, bit 3, pwm 3, address 1. 13 a0 address 0. 14 v ss ground connection. 15 gport2_bit2_pwm0/wd port 2, bit 2, pwm 0, e 2 write disable. 16 int 17 gport2_bit1_pwm0/a2 port 2, bit 1, pwm 0, address 2. 18 gport2_bit0_pwm2/a3 port 2, bit 0, pwm 2, address 3. 19 xres active high external reset with internal pull down. 20 gport1_bit7_pwm0/a4 port 1, bit 7, pwm 0, address 4. 21 gport1_bit6_pwm2/a5 port 1, bit 6, pwm 2, address 5. 22 gport1_bit5_pwm0/a6 port 1, bit 5, pwm 0, address 6. 23 gport1_bit4_pwm2 port 1, bit 4, pwm 2. 24 gport1_bit3_pwm0 port 1, bit 3, pwm 0. 25 gport1_bit2_pwm2 port 1, bit 2, pwm 2. 26 gport1_bit1_pwm0 port 1, bit 1, pwm 0. 27 gport1_bit0_pwm2 port 1, bit 0, pwm 2. 28 v dd supply voltage. gport0_bit0_pwm3 gport0_bit1_pwm1 gport0_bit2_pwm3 gport0_bit3_pwm1 gport0_bit4_pwm3 gport0_bit5_pwm1 gport0_bit6_pwm3 gport0_bit7_pwm1 vss i2c serial clock (scl) i2c serial data (sda) gport2_bit3_pwm3/a1 a0 vss vdd gport1_bit0_pwm2 gport1_bit1_pwm0 gport1_bit2_pwm2 gport1_bit3_pwm0 gport1_bit4_pwm2 gport1_bit5_pwm0/a6 gport1_bit6_pwm2/a5 gport1_bit7_pwm0/a4 xres gport2_bit0_pwm2/a3 gport2_bit1_pwm0/a2 int gport2_bit2_pwm0/wd ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 6 of 32 48-pin part pinout table 5. 48-pin part pinout (ssop) pin no. pin name description figure 3. cy8c9540a 48-pin device 1 gport0_bit0_pwm7 port 0, bit 0, pwm 7. 2 gport0_bit1_pwm5 port 0, bit 1, pwm 5. 3 gport0_bit2_pwm3 port 0, bit 2, pwm 3. 4 gport0_bit3_pwm1 port 0, bit 3, pwm 1. 5 gport0_bit4_pwm7 port 0, bit 4, pwm 7. 6 gport0_bit5_pwm5 port 0, bit 5, pwm 5. 7 gport0_bit6_pwm3 port 0, bit 6, pwm 3. 8 gport0_bit7_pwm1 port 0, bit 7, pwm 1. 9 gport3_bit0_pwm7 port 3, bit 0, pwm 7. 10 gport3_bit1_pwm5 port 3, bit 1, pwm 5. 11 gport3_bit2_pwm3 port 3, bit 2, pwm 3. 12 gport3_bit3_pwm1 port 3, bit 3, pwm 1. 13 v ss ground connection. 14 gport3_bit4_pwm7 port 3, bit 4, pwm 7. 15 gport3_bit5_pwm5 port 3, bit 5, pwm 5. 16 gport3_bit6_pwm3 port 3, bit 6, pwm 3. 17 gport3_bit7_pwm1 port 3, bit 7, pwm 1. 18 gport5_bit2_pwm3 port 5, bit 2, pwm 3. 19 gport5_bit3_pwm1 port 5, bit 3, pwm 1. 20 i 2 c serial clock (scl) i 2 c clock. 21 i 2 c serial data (sda) i 2 c data. 22 gport2_bit3_pwm3/a1 port 2, bit 3, pwm 3, address 1. 23 a0 address 0. 24 v ss ground connection. 25 gport2_bit2_pwm0/wd port 2, bit 2, pwm 0, e 2 write disable. 26 int 27 gport2_bit1_pwm4/a2 port 2, bit 1, pwm 4, address 2. 28 gport2_bit0_pwm6/a3 port 2, bit 0, pwm 6, address 3. 29 gport5_bit1_pwm0 port 5, bit 1, pwm 0. 30 gport5_bit0_pwm2 port 5, bit 0, pwm 2. 31 gport4_bit7_pwm0 port 4, bit 7, pwm 0. 32 gport4_bit6_pwm2 port 4, bit 6, pwm 2. 33 gport4_bit5_pwm4 port 4, bit 5, pwm 4. 34 gport4_bit4_pwm6 port 4, bit 4, pwm 6. 35 xres active high external reset with internal pull down. 36 gport4_bit3_pwm0 port 4, bit 3, pwm 0. 37 gport4_bit2_pwm2 port 4, bit 2, pwm 2. 38 gport4_bit1_pwm4 port 4, bit 1, pwm 4. 39 gport4_bit0_pwm6 port 4, bit 0, pwm 6. 40 gport1_bit7_pwm0/a4 port 1, bit 7, pwm 0, address 4. 41 gport1_bit6_pwm2/a5 port 1, bit 6, pwm 2, address 5. 42 gport1_bit5_pwm4/a6 port 1, bit 5, pwm 4, address 6. 43 gport1_bit4_pwm6 port 1, bit 4, pwm 6. 44 gport1_bit3_pwm0 port 1, bit 3, pwm 0. 45 gport1_bit2_pwm2 port 1, bit 2, pwm 2. 46 gport1_bit1_pwm4 port 1, bit 1, pwm 4. 47 gport1_bit0_pwm6 port 1, bit 0, pwm 6. 48 v dd supply voltage. ssop gport0_bit0_pwm7 vdd gport0_bit1_pwm5 gport1_bit0_pwm6 gport0_bit2_pwm3 gport1_bit1_pwm4 gport0_bit3_pwm1 gport1_bit2_pwm2 gport0_bit4_pwm7 gport1_bit3_pwm0 gport0_bit5_pwm5 gport1_bit4_pwm6 gport0_bit6_pwm3 gport1_bit5_pwm4/a6 gport0_bit7_pwm1 gport1_bit6_pwm2/a5 gport3_bit0_pwm7 gport1_bit7_pwm0/a4 gport3_bit1_pwm5 gport4_bit0_pwm6 gport3_bit2_pwm3 gport4_bit1_pwm4 gport3_bit3_pwm1 gport4_bit2_pwm2 vss gport4_bit3_pwm0 gport3_bit4_pwm7 xres gport3_bit5_pwm5 gport4_bit4_pwm6 gport3_bit6_pwm3 gport4_bit5_pwm4 gport3_bit7_pwm1 gport4_bit6_pwm2 gport5_bit2_pwm3 gport4_bit7_pwm0 gport5_bit3_pwm1 gport5_bit0_pwm2 i2c serial clock (scl) gport5_bit1_pwm0 i2c serial data (sda) gport2_bit0_pwm6/a3 gport2_bit3_pwm3/a1 gport2_bit1_pwm4/a2 a0 int vss gport2_bit2_pwm0/wd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25 [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 7 of 32 100-pin part pinout table 6. 100-pin part pinout (tqfp) pin no. name description pin no. name description 1 dnu dnu = do not use; leave floating. 51 dnu dnu = do not use; leave floating. 2 dnu dnu = do not use; leave floating. 52 gport5_bit1_pwm8 port 5, bit 1, pwm 8. 3 gport0_bit3_pwm1 port 0, bit 3, pwm 1. 53 gport5_bit0_pwm10 port 5, bit 0, pwm 10. 4 gport0_bit4_pwm7 port 0, bit 4, pwm 7. 54 gport5_bit4_pwm12 port 5, bit 4, pwm 12. 5 gport0_bit5_pwm5 port 0, bit 5, pwm 5. 55 gport5_bit5_pwm14 port 5, bit 5, pwm 14. 6 gport0_bit6_pwm3 port 0, bit 6, pwm 3. 56 gport4_bit7_pwm8 port 4, bit 7, pwm 8. 7 gport0_bit7_pwm1 port 0, bit 7, pwm 1. 57 gport4_bit6_pwm10 port 4, bit 6, pwm 10. 8 gport3_bit0_pwm7 port 3, bit 0, pwm 7. 58 gport4_bit5_pwm12 port 4, bit 5, pwm 12. 9 gport3_bit1_pwm5 port 3, bit 1, pwm 5. 59 gport4_bit4_pwm14 port 4, bit 4, pwm 14. 10 gport3_bit2_pwm3 port 3, bit 2, pwm 3. 60 dnu dnu = do not use; leave floating. 11 gport3_bit3_pwm1 port 3, bit 3, pwm 1. 61 dnu dnu = do not use; leave floating. 12 dnu dnu = do not use; leave floating. 62 xres active high external reset with internal pull down. 13 dnu dnu = do not use; leave floating. 63 gport4_bit3_pwm0 port 4, bit 3, pwm 0. 14 dnu dnu = do not use; leave floating. 64 gport4_bit2_pwm2 port 4, bit 2, pwm 2. 15 v ss ground connection. 65 v ss ground connection. 16 gport3_bit4_pwm15 port 3, bit 4, pwm 15. 66 gport4_bit1_pwm4 port 4, bit 1, pwm 4. 17 gport3_bit5_pwm13 port 3, bit 5, pwm 13. 67 gport4_bit0_pwm6 port 4, bit 0, pwm 6. 18 gport3_bit6_pwm11 port 3, bit 6, pwm 11. 68 gport1_bit7_pwm0/a4 port 1, bit 7, pwm 0, address 4. 19 gport3_bit7_pwm9 port 3, bit 7, pwm 9. 69 gport1_bit6_pwm2/a5 port 1, bit 6, pwm 2, address 5. 20 gport5_bit7_pwm15 port 5, bit 7, pwm 15. 70 gport1_bit5_pwm4/a6 port 1, bit 5, pwm 4, address 6. 21 gport5_bit6_pwm13 port 5, bit 6, pwm 13. 71 dnu dnu = do not use; leave floating. 22 gport5_bit2_pwm11 port 5, bit 2, pwm 11. 72 gport1_bit4_pwm6 port 1, bit 4, pwm 6. 23 gport5_bit3_pwm9 port 5, bit 3, pwm 9. 73 dnu dnu = do not use; leave floating. 24 i 2 c serial clock (scl) i 2 c clock. 74 gport1_bit3_pwm0 port 1, bit 3, pwm 0. 25 dnu dnu = do not use; leave floating. 75 dnu dnu = do not use; leave floating. 26 dnu dnu = do not use; leave floating. 76 dnu dnu = do not use; leave floating. 27 dnu dnu = do not use; leave floating. 77 gport1_bit2_pwm2 port 1, bit 2, pwm 2. 28 i 2 c serial data (sda) i 2 c data. 78 dnu dnu = do not use; leave floating. 29 gport2_bit3_pwm11/a1 port 2, bit 3, pwm 11, address 1. 79 gport1_bit1_pwm4 port 1, bit 1, pwm 4. 30 a0 address 0. 80 dnu dnu = do not use; leave floating. 31 dnu dnu = do not use; leave floating. 81 gport1_bit0_pwm6 port 1, bit 0, pwm 6. 32 v dd supply voltage. 82 v dd supply voltage. 33 dnu dnu = do not use; leave floating. 83 v dd supply voltage. 34 v ss ground connection. 84 v ss ground connection. 35 dnu dnu = do not use; leave floating. 85 v ss ground connection. 36 gport7_bit7_pwm15 port 7, bit 7, pwm 15. 86 gport6_bit0_pwm0 port 6, bit 0, pwm 0. 37 gport7_bit6_pwm14 port 7, bit 6, pwm 14. 87 gport6_bit1_pwm1 port 6, bit 1, pwm 1. 38 gport7_bit5_pwm13 port 7, bit 5, pwm 13. 88 gport6_bit2_pwm2 port 6, bit 2, pwm 2. 39 gport7_bit4_pwm12 port 7, bit 4, pwm 12. 89 gport6_bit3_pwm3 port 6, bit 3, pwm 3. 40 gport7_bit3_pwm11 port 7, bit 3, pwm 11. 90 gport6_bit4_pwm4 port 6, bit 4, pwm 4. 41 gport7_bit2_pwm10 port 7, bit 2, pwm 10. 91 gport6_bit5_pwm5 port 6, bit 5, pwm 5. 42 gport7_bit1_pwm9 port 7, bit 1, pwm 9. 92 gport6_bit6_pwm6 port 6, bit 6, pwm 6. 43 gport7_bit0_pwm8 port 7, bit 0, pwm 8. 93 gport6_bit7_pwm7 port 6, bit 7, pwm 7. 44 gport2_bit2_pwm8/wd port 2, bit 2, pwm 8, e 2 write disable. 94 dnu dnu = do not use; leave floating. 45 int 95 gport0_bit0_pwm7 port 0, bit 0, pwm 7. 46 gport2_bit1_pwm12/a2 port 2, bi t 7, pwm 0, address 4. 96 dnu dnu = do not use; leave floating. 47 gport2_bit0_pwm14/a3 port 2, bit 6, pwm 2, address 5. 97 gport0_bit1_pwm5 port 0, bit 1, pwm 5. 48 dnu dnu = do not use; leave floating. 98 dnu dnu = do not use; leave floating. 49 dnu dnu = do not use; leave floating. 99 gport0_bit2_pwm3 port 0, bit 2, pwm 3. 50 dnu dnu = do not use; leave floating. 100 dnu dnu = do not use; leave floating. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 8 of 32 figure 4. cy8c9560a 100-pin device [2] tqfp dnu a dnu gport0_bit3_pwm1 gport0_bit4_pwm7 gport0_bit5_pwm5 gport0_bit6_pwm3 gport0_bit7_pwm1 gport3_bit0_pwm7 gport3_bit1_pwm5 gport3_bit2_pwm3 gport3_bit3_pwm1 dnu dnu dnu vss gport3_bit4_pwm15 gport3_bit5_pwm13 gport3_bit6_pwm11 gport3_bit7_pwm9 gport5_bit7_pwm15 gport5_bit6_pwm13 gport5_bit2_pwm11 gport5_bit3_pwm9 i2c serial clock (scl) dnu dnu vss gport7_bit3_pwm11 gport2_bit1_pwm12/a2 dnu i2c serial data (sda) gport2_bit3_pwm11/a1 a0 dnu vdd dnu dnu gport7_bit7_pwm15 gport7_bit6_pwm14 gport7_bit5_pwm13 gport7_bit4_pwm12 gport7_bit2_pwm10 gport7_bit1_pwm9 gport7_bit0_pwm8 gport2_bit2_pwm8/wd int gport2_bit0_pwm14/a3 dnu dnu dnu dnu gport1_bit3_pwm0 dnu gport1_bit4_pwm6 dnu gport1_bit5_pwm4/a6 gport1_bit6_pwm2/a5 gport1_bit7_pwm0/a4 gport4_bit0_pwm6 gport4_bit1_pwm4 vss gport4_bit2_pwm2 gport4_bit3_pwm0 xres dnu dnu gport4_bit4_pwm14 gport4_bit5_pwm12 gport4_bit6_pwm10 gport4_bit7_pwm8 gport5_bit5_pwm14 gport5_bit4_pwm12 gport5_bit0_pwm10 gport5_bit1_pwm8 dnu dnu gport0_bit2_pwm3 dnu gport0_bit1_pwm5 dnu gport0_bit0_pwm7 dnu gport6_bit7_pwm7 gport6_bit6_pwm6 gport6_bit5_pwm5 gport6_bit4_pwm4 gport6_bit3_pwm3 gport6_bit2_pwm2 gport6_bit1_pwm1 gport6_bit0_pwm0 vss vss vdd vdd gport1_bit0_pwm6 dnu gport1_bit1_pwm4 dnu gport1_bit2_pwm2 dnu 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 note 2. dnu = do not use; leave floating. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 9 of 32 pin descriptions extendable soft addressing the a0 line defines the corresponding bit of the i 2 c address. this pin must be pulled up or down. if a0 is a strong pull up or a strong pull down (wired through 330 or less resistor to vdd or vss), then that is the only address line being specified and the a1-a6 lines are used as gpio. if a0 is a weak pull up or a weak pull down (connected to vdd or vss through 75k- 200k ohm resistor), then a0 is not the only externally defined address bit. there is a pin assigned to be a1 if it is needed. this pin can be pulled up or pulled down strong or weak with a resistor. as with a0, the type of pull determines whether the address bit is the last externally defined address bit. differently from a0, a1 is not dedicated as an address pin. it is only used if a0 is not the only address bit externally defined. there are also predefined pins for a2, a3, a4, a5, and a6 that is only used for addressing if needed. the last address bit in the chain is pulled strong. that way, only the number of pins needed to assign the address desired for the part are allocated as address pins, any pins not used for address bits can be used as gpio pins. the ta b l e 2 on page 4 defines the resulting device i 2 c address. interrupt pin (int) the interrupt output (if enabled) is activated if one of these events occurs: one of the gpio port pins changes state and the corresponding bit in the interrupt ma sk register is set low. when a pwm driven by the slowest clock source (367.6 hz) and assigned to a pin changes state and the pin?s corre- sponding bit in the interrupt mask register is set low. the interrupt line is deactivated when the master device performs a read from the corresp onding interrupt status register. write disable pin (wd) if this feature is e nabled, ?0? allows wr ites to the eeprom and ?1? blocks any memory writes. th is pin is checked immediately before performing any write to memory. if the eee bit in the enable register is not set (eepr om disabled) or bit eero is set (eeprom is read-only) then wd line level is ignored. note that ?1? on this line blo cks all commands that perform opera- tions with eeprom (see table 15 on page 14). this line may be enabled/disabled by bit 1 of the enable register (2dh): ?1? enables wd function, ?0? disables. external reset pin (xres) a full device reset is caused by pulling the xres pin high. the xres pin has an always-on pull down resistor, so it does not require an external pull down for operation. it can be tied directly to ground or left open. behavior after xres is similar to por. when the part is held in reset, all in and out pins are held at their default high-z state. working with pwms there are four independent pwms in the CY8C9520A, eight in the cy8c9540a and sixteen in the cy8c9560a. each i/o pin can be configured as a pwm out put by writing ?1? to the corre- sponding bit of the select pwm register (see ta b l e 8 on page 12). the next step of pwm configurat ion is clock source selection using the config pwm registers. there are six available clock sources: 32 khz (default), 24 mhz, 1.5 mhz, 93.75 khz, 367.6 hz or previous pwm output. (see figure 5 ) figure 5. clock sources by default, 32 khz is selected as the pwm clock. pwm period registers are used to set the output period: allowed values are between 1 and ffh. the pwm pulse width register sets the duration of the pwm output pulse. allowed values are between zero and the (period-1) value. the duty cycle ratio is computed using thsi equation: di vi der (1-255) 93.75 khz 367.6 hz - 93.75 khz 1.5 mhz 24 mhz 32 khz t out period t clk = dutycycle pulsewidth period ---------------- -------------- = [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 10 of 32 figure 6. memory reading and writing figure 7. port reading and writing in multi-port device s a6 a5 a3 a2 a1 a0 1 a a4 data(addr) a data(addr+1) ack from slave s a6 a5 a3 a2 a1 a0 0 a high(addr) a low(addr) a4 a n p no ack from master stop a ... ack from master ack from master ack from slave ack from slave ack from slave r/w start slave address r/w memory address reading from eeprom data 1 s a6 a5 a3 a2 a1 a0 0 a high(addr) a low(addr) a4 a ack from slave ack from slave ack from slave start r/w writing to eeprom a data 2 a p if current address crosses 64-byte block boundary, then device performs real writing to eeprom stop a ... up to the end of address space memory address slave address s 0 a data from gport1 ... start slave address r/w register address = 1 reading from gport 1 0 0 0 0 0 0 0 1 a s a6 a5 a3 a2 a1 a0 a4 a6 a5 a3 a2 a1 a0 a4 1 a a data from gport 2 a n p no ack from master stop ack from slave ack from slave ack from master r/w at this moment, device performs reading from gport 1 reading from gport 2 s 0 a data from gport1 ... start r/w register address = 09h writing from gport 1 0 0 0 0 1 0 0 1 a a6 a5 a3 a2 a1 a0 a4 a a ack from slave ack from slave ack from slave at this moment, device performs output to gport 1 data from gport 2 data from gport 3 output to gport 2 output to gport 3 a ack from slave p stop slave address [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 11 of 32 register mapping table the register address is auto-incre menting. if the master device writes or reads data to or from one register and then continues data transfer in the same i 2 c transaction, sequential bytes are written or read to or from the following registers. for example, if the first byte is sent to the out put port 1 register, then the next bytes are written to output port 2, output port 3, output port 4 etc. the first byte of each writ e transaction is treated as the register address. to read data from a seires of registers, the master device must write the starting register address byte then perform a start and series of read transactions. if no address was sent, reads start from address 0. to read a specific register addr ess, the master device must write the register address byte, then perform a start and read trans- action. see figure 7 on page 10. the device?s register mapping is listed in ta b l e 7 . register descriptions the registers for the cy8c95xx are described in the sections that follow. note that the pwm registers are located at addresses 28h to 2bh. input port registers (00h - 07h) these registers represent actual logical levels on the pins and are used for i/o port reading operations. they are read only. the inversion registers changes the state of reads to these ports. output port registers (08h - 0fh) these registers are used for writing data to gpio ports. by default, all ports are in the pull up mode allowing quasi-bidirec- tional i/o. to allow input oper ations without reconfiguration, these registers have to store ?1?s. output register data also affects pin states when pwms are enabled. see table 8 on page 12 for details. see figure 7 on page 10 illustrates port read/write procedures. the inversion registers have no effect on these ports. table 7. the device register address map address register default register value 00h input port 0 none 01h input port 1 none 02h input port 2 none 03h input port 3 none 04h input port 4 none 05h input port 5 none 06h input port 6 none 07h input port 7 none 08h output port 0 ffh 09h output port 1 ffh 0ah output port 2 ffh 0bh output port 3 ffh 0ch output port 4 ffh 0dh output port 5 ffh 0eh output port 6 ffh 0fh output port 7 ffh 10h interrupt status port 0 00h 11h interrupt status port 1 00h 12h interrupt status port 2 00h 13h interrupt status port 3 00h 14h interrupt status port 4 00h 15h interrupt status port 5 00h 16h interrupt status port 6 00h 17h interrupt status port 7 00h 18h port select 00h 19h interrupt mask ffh 1ah select pwm for port output 00h 1bh inversion 00h 1ch pin direction - input/output 00h 1dh drive mode - pull up ffh 1eh drive mode - pull down 00h 1fh drive mode - open drain high 00h 20h drive mode - open drain low 00h 21h drive mode - strong 00h 22h drive mode - slow strong 00h 23h drive mode - high-z 00h 24h reserved none 25h reserved none 26h reserved none 27h reserved none 28h pwm select 00h 29h config pwm 00h 2ah period pwm ffh 2bh pulse width pwm 80h 2ch programmable divider ffh 2dh enable wde, eee, eero 00h 2eh device id/status 20h/40h/60h 2fh watchdog 00h 30h command 00h table 7. the device register address map (continued) address register default register value [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 12 of 32 int. status port registers (10h - 17h) each ?1? bit in these registers signals that there was a change in the corresponding input line since the last read of that interrupt status register. each interrupt (i nt.) status register is cleared only after a read of that register. if a pwm is assigned to a pin, then all state changes of the pwm sets the corresponding bit in the interrupt status register. if the pin's interrupt mask is cleared and the pwm is set to the slowest possible rate allowed (driven by the programmable clock source with divide register 2dh set to ffh), then the int line also drives on the pwm state change. port select register (18h) this register configures the gpor t. write a value of 0-7 to this register to select the port to program with registers 19h-23h. interrupt mask port register (19h) the interrupt mask register enables or disables activation of the int line when gpio input levels are changed. each ?1? in the interrupt mask register masks (disables) interrupts generated from the corresponding input line of the gport selected by the port select register (18h). select pwm register (1ah) this register allows each port to act as a pwm output. by default, all ports are configured as gpio lines. each ?1? in this register connects the corresponding pin of the gport selected by the port select register (18h) to the pw m output. output register data also affects the pin state when a pwm is enabled. see ta b l e 8 . note that a pin used as pwm output must be configured to the appropriate drive mode. see table 10 on page 12 for more infor- mation. ta b l e 8 describes the logic of the output and select pwm registers. inversion register (1bh) this register can invert the logi c of the input ports. each ?1? written to this register inverts t he logic of the corresponding bit in the input register of the gport sele cted by the port select register (18h). the input registers' logic is presented in ta b l e 9 . these registers have no effect on outputs or pwms. port direction register (1ch) each bit in a port is configurabl e as either an input or an output. to perform this configuration, t he port direction register (1ch) is used for the gport selected by the port select register (18h). if a bit in this register is set (wri tten with '1'), the corresponding port pin is enabled as an input. if a bit in this register is cleared (written with '0'), the corresponding port pin is enabled as an output. drive mode registers (1dh-23h) each port's data pins can be set separately to one of seven available modes: pull up or down, open drain high/low, strong drive fast/slow, or high-impedance input. to perform this config- uration, the seven drive mode registers are used for the gport selected by the port select regist er (18h). each ?1? written to this register changes the correspondi ng line drive mode. registers 1dh through 23h have last register priority meaning that the bit set to high in which the last register was written overrides those that came before. reading these registers reflects the actual setting, not what was originally written. pwm select register (28h) this register is configures the pwm. write a value of 00h-0fh to this register to select the pwm to program with registers 29h-2bh. table 8. output and se lect pwm registers logic output select pwm pin state 000 101 010 1 1 current pwm table 9. inversion register logic pin state invert input 000 101 011 110 table 10. drive mode register settings reg. pin state description 1dh resistive pull up resistive high, strong low (default) 1eh resistive pull down strong high, resistive low 1fh open drain high slow strong high, high z low 20h open drain low slow strong low, high z high 21h strong drive strong high, strong low, fast output mode 22h slow strong drive strong high, strong low, slow output mode 23h high impedance high z [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 13 of 32 config (29h) this register selects the clo ck source for the pwm selected by the pwm select register (28h) and interrupt logic. there are six available clock sources: 32 khz (default), 24 mhz, 1.5 mhz, 93.75 khz, 367.6 hz , or previous pwm output. the 367.6 hz clock is user programmable. it divides the 93.75 khz clock source by the divisor stor ed in the divider register (2ch). the default divide ratio is 255. (see table 11 for details). by default, all pwms are clocked from 32 khz. each pwm can generate an interrupt at the rising or falling edge of the output pulse. there is a lim itation on the clock source for a pwm to generate an interrupt. only the slowest speed source (programmed to 367.6 hz) with the divider equal to 255 allows interrupt generation. consequently, to create a pwm interrupt, it is necessary to choose the programmable divider output as the clock source (write xxxxx100b to config register (29h)), write 255 to the divide register (2ch), and select pwm for pin output (1ah). interrupt status is reflected in the interrupt status registers (10h-17h) and can cause int line activation if enabled by the corresponding mask bit in th e interrupt mask register: period register (2ah) this register sets the period of the pwm counter. allowed values are between 1 and ffh. the effective output waveform period of the pwm is: pulse width register (2bh) this register sets the pulse width of the pwm output. allowed values are between zero and the (period - 1) value. the duty cycle ratio can be computed us ing the following equation: divider register (2ch) this register sets the frequency on the output of the program- mable divider: allowed values are between 1 and 255. enable register (2dh) the wde bit configures the write disable pin to operate either as a gpio or as wd. it also enables/disables eeprom operations (eee bit) or makes the eeprom read-only (eero bit). bit assignments are shown in table 13 on page 13. each ?1? enables the corresponding feature, ?0? disables. writes to this register differ from other registers. the write sequence to modify the enable register is as follows: 1. send device i 2 c address with bit 0. 2. send register address 2dh. 3. send unlock key - the sequence of three bytes: 43h, 4dh, 53h; ('c', 'm', 's' in ascii bytes). 4. send new enable register value. this write sequence secures the register from accidental changes. the register can be re ad without the use of the unlock key. by default, eero and eeprom (eee bit) are disabled and wd line (wde bit) is set to gpio (wd disabled). when performing a burst write operation that crosses this register, the data written to this register is ignored and the address increments to 2eh. device id/status register (2eh) this register stores device identifiers (2xh/4xh/6xh) and reflects which settings were loaded during startup, either factory defaults (fd) or user defaults (ud). by default during startup, the device attempts to load the user default block. if it is corrupted then factory defaults are loaded and the lo w nibble of this register is set high to inform which set is active. the high nibble is always equal to 2 for CY8C9520A, 4 for cy8c9540a, and 6 for cy8c9560a. this register is read-only. table 11. pwm clock sources config pwm pwm clock source xxxxx000b 32 khz (default) xxxxx001b 24 mhz xxxxx010b 1.5 mhz xxxxx011b 93.75 khz xxxxx100b 367.6 hz (programmable) xxxxx101b previous pwm table 12. period register config pwm pwm interrupt on xxxx0xxxb falling pulse edge (default) xxxx1xxxb rising pulse edge out clk tperiodt =? . pulsewidth dutycycle period = table 13. enable register bit 7 6 5 4 3 2 1 0 function reserved eero eee wde default reserved 0 0 0 table 14. device id status register bit 7 6 5 4 3 2 1 0 function device family (2, 4,or 6) reserved fd/ud 93.75 . khz frequency divider = [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 14 of 32 watchdog register (2fh) this register controls the inter nal watchdog timer. this timer can trigger a device reset if the device is not responding to i 2 c requests due to misconfigurati on. device operation is not affected when the watchdog register = 0. if the i 2 c master writes any non zero value to the watchdog register, the countdown mechanism is activated and each second the register is decre- mented. upon transition from 1 to 0, the device is rebooted, which restores user defaults. af ter reboot, the watchdog register value is reset to zero. any i 2 c transaction (addressing the expander) resets the watchdog regi ster to the previously stored value. any device reboot (caused by a por or watchdog) sets the watchdog register to zero (turns off the watchdog feature). the watchdog timer can be disabled by writing zero to the watchdog register (2fh) or by using the reconfigure device cmd (07h). note the watchdog timer is not intended to track precise time intervals. the timer's frequency can vary in range between -50% on up to +100%. this variation must be taken into account when selecting the appropriate val ue for the watchdog register. command register (30h) this register sends commands to the device, including current configuration as new por defaul ts, restore factory defaults, define por defaults, read por de faults, write device configu- ration, read device configuration, and reconfigure device with stored por defaults. the command set is presented in ta b l e 1 5 . note registers are not restored in parallel. do not assume any particular order to the restoration process. commands description store config to e 2 por defaults cmd (01h) the current ports settings (drive modes and output data) and other configuration re gisters are saved in the eeprom by using the store configuration command (cmd). these settings are automatically loaded after the next device power up or if the 07h command is issued. restore factory defaults cmd (02h) this command replaces the save d user configuration with the factory default configuration. cu rrent settings are unaffected by this command. new settings are loaded after the next device power up or if the 07h command is issued. write e 2 por defaults cmd (03h) this command sends new power up defaults to the cy8c95xx without changing current sett ings unless the 07h command is issued afterwards. this command is followed by 147 data bytes according to table 16 . the crc is calculated as the xor of the 146 data bytes (00h-91h). if the crc check fails or an incom- plete block is sent, then the slave responds with a nak and the data does not get saved to eeprom. to define new por defaults the user must: write command 03h write 146 data bytes with new values of registers write 1 crc byte calculated as xor of previous 146 data bytes. content of the data block is described in ta b l e 1 6 . table 15. available commands command description 01h store device configuration to eeprom por defaults 02h restore factory defaults 03h write eeprom por defaults 04h read eeprom por defaults 05h write device configuration 06h read device configuration 07h reconfigure device with stored por defaults table 16. por defaults data structure offset value 00h ? 07h output port 0-7 08h ? 0fh interrupt mask port 0-7 10h ? 17h select pwm port 0-7 18h ? 1fh inversion port 0-7 20h ? 27h pin direction port 0-7 28h resistive pull up drive mode port 0 29h resistive pull down drive mode port 0 2ah open drain high drive mode port 0 2bh open drain low drive mode port 0 2ch strong drive drive mode port 0 2dh slow strong drive drive mode port 0 2eh high impedance drive mode port 0 2fh ? 35h drive modes port 1 36h ? 3ch drive modes port 2 3dh ? 43h drive modes port 3 44h ? 4ah drive modes port 4 4bh ? 51h drive modes port 5 52h ? 58h drive modes port 6 59h ? 5fh drive modes port 7 60h config setting pwm0 61h period setting pwm0 62h pulse width setting pwm0 63h ? 65h pwm1 settings ?? 8dh ? 8fh pwm15 settings 90h divider 91h enable 92h crc [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 15 of 32 read e2 por defaults cmd (04h) this command reads the por settings stored in the eeprom. to read por defaults the user must: write command 04h read 146 data bytes (see ta b l e 1 6 ) read 1 crc byte. write device config cmd (05h) this command sends a new device configuration to the cy8c95xx. it is followed by 146 data bytes according to ta b l e 1 6 . the crc is calculated as the xor of the 146 data bytes (00h-91h). if the crc check fails or an incomplete block is sent, then the slave responds with a nak and the device does not use the data. this gives the user ?flat-address-space? access to all device settings. to set the current device configuration the user must: write command 05h write 146 data bytes with new values of registers write 1 crc byte calculated as xor of previous 146 data bytes. if the crc check passes, then the device uses the new settings immediately. content of the data block is described in ta b l e 1 6 . read device config cmd (06h) this command reads the current device configuration. it gives the user ?flat-address-space? access to all de vice settings. to read device configuration the user must: write command 06h read 146 data bytes (see table 16 ). read 1 crc byte. reconfigure device cmd (07h) this command immediately reco nfigures the device with actual por defaults from eeprom. it has the same effect on the registers as a por. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 16 of 32 electrical specifications this section lists the dc and ac electrical specifications of the cy8c95xxa device. fo r the most up to date electrical specific ations, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. specifications are valid for -40 c t a 85 c and t j 100 c, except where noted. ta b l e 1 7 lists the units of measure that are used in this section. absolute maximum ratings operating temperature table 17. units of measure symbol unit of measure symbol unit of measure c degree celsius ma milli-ampere khz kilohertz na nanoampere mhz megahertz ns nanosecond s microsecond pf picofarad v microvolts v volts vrms microvolts root-mean-square table 18. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduces data retention time. recommended storage temper- ature is +25 c 25 c. extended duration storage temperatures above 65 c degrades reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current in to any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 19. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see ?thermal imped- ances per package? on page 23 . the user must limit the power consumption to comply with this requirement. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 17 of 32 dc electrical characteristics dc chip-level specifications table 20 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. dc i 2 c specifications ta b l e 2 4 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 20. CY8C9520A dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current vdd 5v ? 3.8 5 ma conditions are 5.0v, t a = 25 c, ioh = 0. i dd3 supply current vdd 3.3v ? 2.3 3 ma conditions are 3.3v, t a = 25 c, ioh = 0. table 21. cy8c9540a dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current vdd 5v ? 6 9 ma conditions are 5.0v, t a = 25 c, ioh = 0. i dd3 supply current vdd 3.3v ? 3.3 6 ma conditions are 3.3v, t a = 25 c, ioh = 0. table 22. cy8c9560a dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current vdd 5v ? 15 25 ma conditions are 5.0v, t a = 25 c, ioh = 0. i dd3 supply current vdd 3.3v ? 5 9 ma conditions are 3.3v, t a = 25 c, ioh = 0. table 23. dc programming specifications symbol description min typ max units notes flash enpb flash (eeprom) endurance (by block) 10,000 ? ? ? erase/write cycles by block. flash ent flash endurance (total) [3] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years table 24. dc i 2 c specifications [4] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 3.0 v v dd 3.6 v ? ? 0.25 v dd v 4.75 v v dd 5.25 v v ihi2c input high level 0.7 v dd ? ? v 3.0 v v dd 5.25 v note 3. a maximum of 180 x 10,000 block endurance cycles is allowed. th is may be balanced between operations on 180x1 blocks of 10,00 0 maximum cycles each, 180x2 blocks of 5,000 maximum cycles each, or 180x4 blocks of 2,500 maximu m cycles each (to limit the total number of cycles to 180x1 0,000 and that no single block ever sees more than 10,000 cycles). 4. all gpio meet the dc gpio vil and vih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 18 of 32 dc gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 25. dc gpio specifications symbol description min typ max units notes v oh high output level vdd - 1.0 ? ? v i oh = 10 ma for any one pin, vdd = 4.75 to 5.25v. 40 ma maximum combined ioh for gport0; gport2_bit3; gport3; gport5_bit2, 3, 6, 7; gport6. 40 ma maximum combined ioh for gport1; gport2_bit0, 1, 2; gport4; gport5_bit0, 1, 4, 5; gport7. 80 ma maximum combined ioh. v ol low output level ? ? 0.75 v i ol = 25 ma for any one pin, vdd = 4.75 to 5.25v. 100 ma maximum combined io l for gport0; gport2_bit3; gport3; gport5_bit2, 3, 6, 7; gport6. 100 ma maximum combined i ol for gport1; gport2_bit0, 1, 2; gport4; gport5_bit0, 1, 4, 5; gport7. 200 ma maximum combined i ol . i oh high level source current 10 ? ? ma v oh = vdd-1.0v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v vdd = 3.0 to 5.5. v ih input high level 2.1 ? ? v vdd = 3.0 to 5.5. i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 19 of 32 ac electrical characteristics ac gpio specifications table 26 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 8. gpio timing diagram ac pwm specifications table 27 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 26. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls trisef trises 90% 10% gpio pin output voltage table 27. ac pwm specifications symbol description min typ max units notes jitter24mhzpwm 24 mhz based pwm peak-to-peak period jitter ? 0.1 1.5 % 24 mhz, 1.5 mhz, 93.75 khz and 367.6 hz (programmable) sources. jitter32khzpwm 32 khz-based pwm peak-to-peak period jitter ? 2.5 5.0 % 32 khz clock source. f24mhzpwm input frequency of 24 mhz based pwm 23.4 24 24.6 mhz f32khzpwm input frequency of 32 khz based pwm 15 32 64 khz f1.5mhzpwm input frequency of 1.5 mhz based pwm 1.46 1.5 1.53 mhz f93.75khzpwm input frequen cy of 93.75 khz based pwm 91.40 93.75 96.09 khz [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 20 of 32 ac i 2 c specifications table 28 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 9. definition for timing for fast/standard mode on the i 2 c bus ac eeprom write specifications table 29 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 28. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 ? khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeat ed start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 3 ?ns t sustoi2c setup time for st op condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?0?ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition table 29. ac eeprom write specifications symbol description min typ max units notes t eepromwrite_hot eeprom erase + write time ? ? 100 ms 0c tj 100c t eepromwrite_cold eeprom erase + write time ? ? 200 ms -40c tj 0c [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 21 of 32 packaging dimensions this section illustrates the packaging specif ications for the cy8c95xxa device, along with the thermal impedances for each pack age and the solder reflow peak temperature. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refe r to the emulator pod drawings at http://www.cypress.com . figure 10. 28-pin (210-mil) ssop 51-85079 *d [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 22 of 32 figure 11. 48-pin (300-mil) ssop figure 12. 100-pin (14 x 14 x 1.0 mm) tqfp 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 51-85061 *d 51-85048 *d [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 23 of 32 thermal impedances solder reflow peak temperature table 31 lists the minimum solder reflow peak temperature to achieve good solderability. table 30. thermal impedances per package package typical ja [5] 28 ssop 101 c/w 48 ssop 69 c/w 100 tqfp 48 c/w table 31. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28 ssop 260 c 20 s 48 ssop 260 c 20 s 100 tqfp 260 c 20 s notes 5. t j = t a + power x ja. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 24 of 32 features and ordering information table 32 lists the cy8c95xxa device?s key package features and ordering codes. a definition of the ordering number code follows. ordering code definitions table 32. cy8c95xxa device key features and ordering information package ordering code [6] eeprom (bytes) temperature range pwm sources configurable i/o pins 28 pin (210 mil) ssop CY8C9520A-24pvxi 3k -40 c to +85 c 4 20 28 pin (210 mil) ssop (tape and reel) CY8C9520A-24pvxit 3k -40 c to +85 c 4 20 48 pin (300 mil) ssop cy8c9540a-24pvxi 11k -40 c to +85 c 8 40 48 pin (300 mil) ssop (tape and reel) cy8c9540a-24pvxit 11k -40 c to +85 c 8 40 100 pin tqfp cy8c9560a-24axi 27k -40 c to +85 c 16 60 100 pin tqfp (tape and reel) cy8c9560a-24axit 27k -40 c to +85 c 16 60 note 6. the a after the existing port expander pa rt number indicates new device firmware. cy 8 c 9 xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx/ltx/lqx/lcx = qfn pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 25 of 32 acronyms ta b l e 3 3 lists the acronyms that are used in this document. reference documents communication ? i 2 c port expander with flash storage ? an2304 (001-27119) document conventions units of measure ta b l e 3 4 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 33. acronyms used in this datasheet acronym description acronym description ac alternating current por power on reset api application programming interface psoc ? programmable system-on-chip cmos complementary metal oxide semiconductor pwm pulse width modulator crc cyclic redundancy check ssop s hrink small-outline package dc direct current tqfp thin quad flat pack eeprom electrically erasable programmable read-only memory uart universal asynchronous reciever / transmitter gpio general purpose i/o usb universal serial bus msb most-significant bit wdt watchdog timer pcb printed circuit board xres external reset table 34. units of measure symbol unit of measure symbol unit of measure c degree celsius na nanoampere pf picofarad s microsecond hz hertz ms millisecond khz kilohertz ns nanosecond mhz megahertz v volts k kilohm w watt ohm mm millimeter a microampere % percent ma milliampere [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 26 of 32 glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 27 of 32 compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. glossary (continued) [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 28 of 32 ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses vdd and provides an interrupt to the system when vdd falls below a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. glossary (continued) [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 29 of 32 port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is below a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. glossary (continued) [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 30 of 32 tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
CY8C9520A cy8c9540a, cy8c9560a document number: 38-12036 rev. *e page 31 of 32 document history page document title: CY8C9520A, cy8c9540a, cy8c9560a , 20, 40, and 60 bit i/o expander with eeprom document number: 38-12036 revision ecn no. orig. of change submission date description of change ** 346754 hmt see ecn new silicon, document. *a 392484 hmt see ecn correct pin 79 on the tqfp. add ac pwm output jitter spec. table. upgrade to cy perform logo and update zip code and trademarks. *b 1336984 hmt/aesa see ecn update typical and recommended stora ge temperature per industrial specs. update copyright and trademarks. add watchdog timer details. add ?a? to existing part numbers to indicate new firmware. fix errors. implement cy template. *c 2843174 yara 01/08/2010 added contents. updated overview . updated pin 11 description in figure 2 on page 5. modified note 3. added i oh and i ol specifications in dc gpio specifications . removed ?output jitter? from ac pwm specifications section on page 18. added f24mhzpwm, f32k hzpwm, and f93.5khzpwm specifi- cations in ta b l e 2 7 . added table 29 . *d 2903402 njf 04/01/2010 updated cypress website links added t baketemp and t baketime parameters updated package diagrams *e 3110285 njf 12/14/10 added text ?when the part is held in reset all in and out pins are held at their default high-z state? to section ?external reset pin (xres)? on page 9. added dc i 2 c specifications table. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes made to i 2 c timing diagram. it has been updated for clearer understanding. [+] feedback
document number: 38-12036 rev. *e revised december 14, 2010 page 32 of 32 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed associat ed companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from octo ber 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. CY8C9520A cy8c9540a, cy8c9560a ? cypress semiconductor corporation, 2007-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY8C9520A

	To Download CY8C9520A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .